This invention relates to the field of integrated circuit fabrication. More particularly, this invention relates to integrated circuit characterization based upon the amount of thermal energy to which the integrated circuit is exposed.
Integrated circuits, such as those based upon semiconductor technology like silicon, germanium, and III-IV compounds, tend to be sensitive to the amount of thermal energy that they are exposed to. For example, as a part of the fabrication process for some integrated circuits, certain atomic species, generally referred to as dopants, are introduced into the integrated circuit to form various structures. One specific method for doing this is ion implantation, where the dopant species is accelerated toward the integrated circuit substrate, and driven into the surface of the integrated circuit substrate by the momentum of the accelerated species.
The initial nominal depth of the dopant below the surface of the substrate and the distribution of the dopant about that nominal depth are carefully controlled so as to eventually result in a dopant profile that enables the portion of the substrate so effected to behave according to a set of desired electrical properties. As a part of this process, the dopant is typically thermally activated in some manner. Most often, this thermal activation is accomplished with an anneal of some type, such as a rapid thermal anneal or a furnace anneal.
The amount of thermal energy to which the integrated circuit is exposed tends to be critical, as it effects the dopant profile. The amount of such thermal energy is most easily controlled by controlling the temperatures to which the integrated circuit is exposed and the length of time at which the integrated circuit is exposed to the temperatures. Thus, post doping anneals are carefully controlled as to length of time of exposure and temperature of exposure.
However, there are other processes to which the integrated circuit is necessarily exposed after such thermal energy sensitive operations, which also expose the integrated circuit to thermal energy. Thus, such subsequent processes are generally accounted for during the doping and annealing processes, so that the final structures created at completion of the fabrication process perform as desired. Unfortunately, different integrated circuits tend to require different processing steps, which situation tends to require that many, many different processes be used for early formation of the structures, so as to account for the many different processing tracks that will selectively be used for final processing steps.
Although the above issues have been presented with specific reference to the example of implantation of a dopant as the thermally sensitive operation, it is appreciated that there are many such thermal energy sensitive operations that are performed and structures that are created during fabrication of the integrated circuit. For further example, many materials that are formed into adjacent structures tend to inter diffuse one into the other as thermal energy is absorbed through subsequent processing. Such inter diffusion, if not properly accounted for, tends to change the critical and desirable characterizations of the integrated circuit, such as electrical and physical characterizations.
What is needed, therefore, is a method for processing integrated circuits where earlier processes can be standardized regardless of the subsequent processing of the integrated circuit.
The above and other needs are met by a method of standardizing a fabrication process for an integrated circuit. The fabrication process includes a preceding thermal energy sensitive process and at least one set of selectable succeeding thermal energy delivery processes. Each one of the set of selectable succeeding thermal energy delivery processes delivers different amounts of thermal energy to the integrated circuit, where one of the different amounts of thermal energy is a greatest amount of thermal energy.
An integrated circuit structure is formed using the preceding thermal energy sensitive process. The preceding thermal energy sensitive process is characterized based at least in part upon the greatest amount of thermal energy delivered to the integrated circuit by one of the set of selectable succeeding thermal energy delivery processes. In the case where one of the set of selectable succeeding thermal energy delivery processes is selected that delivers an actual amount of thermal energy to the integrated circuit that is less than the greatest amount of thermal energy, an additional amount of thermal energy is delivered to the integrated circuit. The additional amount of thermal energy is equal to a difference between the actual amount of thermal energy and the greatest amount of thermal energy.
In this manner, the preceding thermal energy sensitive process preferably requires only a single configuration that takes into account the amount of thermal energy that will be subsequently delivered to the integrated circuit. Then as subsequent processes are selected and accomplished, if they do not deliver the greatest amount of thermal energy as anticipated by the preceding thermal energy sensitive process, an additional amount of thermal energy is added, so as to preferably equal the anticipated greatest amount of thermal energy. In this manner, the characterization of the preceding thermal energy sensitive process attains its desired parameters, regardless of the amount of thermal energy actually delivered by the subsequent process.
In various preferred embodiments, the at least one set of selectable succeeding thermal energy delivery processes includes deposition anneal process and oxidation processes, such as gate oxidation processes. The preceding thermal energy sensitive process preferably includes implantation of a dopant, fabrication of a transistor junction, and fabrication of an inter diffused region between two adjacent dissimilar material layers, such as a silicide region. Most preferably, the additional amount of thermal energy is delivered to the integrated circuit as a thermal anneal in a chemically non reactive environment.